Laminated wiring board

ABSTRACT

A laminated wiring board includes a plurality of first wiring boards laminated on one another, a first insulating resin layer disposed between two adjacent first wiring boards among the plurality of first wiring boards, and a second insulating resin layer configured to cover side surfaces of the plurality of first wiring boards.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority to Japanese Patent Application No. 2022-096863, filed on Jun. 15, 2022, the entire contents of which are incorporated herein by reference.

FIELD

Certain aspects of the embodiments discussed herein are related to laminated wiring boards, and methods for manufacturing laminated wiring boards. The laminated wiring board is sometimes also referred to as a multilayer wiring board.

BACKGROUND

A known wiring board includes a plurality of interconnect layers formed on two mutually opposite surfaces of a core layer, for example.

Examples of the wiring board are proposed in Japanese Laid-Open Patent Publication No. 2004-200689, and International Publication Pamphlet No. WO 2014/181766 A1, for example.

As the size of the wiring board increases and the number of interconnect layers included in the wiring board increases, the yield of the wiring board may deteriorate.

SUMMARY

Accordingly, it is an object in one aspect of embodiments to provide a laminated wiring board and a method for manufacturing the laminated wiring board, which can reduce deterioration of the yield.

According to one aspect of the embodiments, a laminated substrate includes a plurality of first wiring boards laminated on one another; a first insulating resin layer disposed between two adjacent first wiring boards among the plurality of first wiring boards; and a second insulating resin layer configured to cover side surfaces of the plurality of first wiring boards.

The object and advantages of the embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a top view illustrating an example of a laminated wiring board according to a first embodiment;

FIG. 2 is a cross sectional view illustrating the example of the laminated wiring board according to the first embodiment;

FIG. 3A and FIG. 3B are cross sectional views (part 1) illustrating examples of wiring boards;

FIG. 4A and FIG. 4B are cross sectional views (part 2) illustrating examples of wiring boards;

FIG. 5 is a cross sectional view (part 3) illustrating an example of a wiring board;

FIG. 6A and FIG. 6B are diagrams (part 1) illustrating an example of a method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 7A and FIG. 7B are diagrams (part 2) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 8A and FIG. 8B are diagrams (part 3) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 9A and FIG. 9B are diagrams (part 4) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 10A and FIG. 10B are diagrams (part 5) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 11A and FIG. 11B are diagrams (part 6) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 12A and FIG. 12B are diagrams (part 7) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 13 is a diagram (part 8) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 14 is a diagram (part 9) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 15 is a diagram (part 10) illustrating the example of the method for manufacturing the laminated wiring board according to the first embodiment;

FIG. 16 is a top view illustrating an example of the laminated wiring board according to a second embodiment;

FIG. 17 is a cross sectional view illustrating the example of the laminated wiring board according to the second embodiment; and

FIG. 18 is a cross sectional view illustrating an example of the laminated wiring board according to a third embodiment.

DESCRIPTION OF EMBODIMENTS

Preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, constituent elements having substantially the same functional configuration are designated by the same reference numerals, and a redundant description thereof may be omitted.

First Embodiment

<Configuration of Laminated Wiring Board>

First, a configuration of a laminated wiring board according to a first embodiment will be described. FIG. 1 is a top view illustrating an example of the laminated wiring board according to the first embodiment. FIG. 2 is a cross sectional view illustrating the example of the laminated wiring board according to the first embodiment. FIG. 2 corresponds to a cross sectional view along a line II-II in FIG. 1 .

As illustrated in FIG. 1 and FIG. 2 , a laminated wiring board 1 according to the first embodiment includes a wiring board 100, a wiring board 200, a wiring board 300, a wiring board 400, a wiring board 500, and an insulating resin layer 700. The wiring boards 200, 300, 400, and 500 are laminated in this order on the wiring board 100.

In the present embodiment, for the sake of convenience, a side on which the wiring board 500 is located when viewed from the wiring board 100 is referred to as an upper side or one side, and a side on which the wiring board 100 is located when viewed from the wiring board 500 is referred to as a lower side or the other side. In addition, a surface of each portion on the side closer to the wiring board 500 than to the wiring board 100 is referred to as an upper surface or one surface, and a surface of each portion on the side closer to the wiring board 100 than to the wiring board 500 is referred to as a lower surface or the other surface. However, the laminated wiring board 1 can be used in an upside-down state, or can be used in a state inclined at an arbitrary angle. A plan view of an object refers to a view of the object in a normal direction to the upper surface of the wiring board 500, and a planar shape of the object refers to a shape of the object in the plan view viewed in the normal direction to the upper surface of the wiring board 500.

The planar shape of each of the wiring boards 100, 200, 300, 400, and 500 is a rectangular shape, for example. In the plan view, the lengths of corresponding sides of the wiring boards 200, 300, 400, and 500 are approximately the same. On the other hand, the lengths of sides of the wiring board 100 are longer than the lengths of the corresponding sides of the wiring boards 200, 300, 400, and 500.

The wiring board 200 is provided on the wiring board 100. The laminated wiring board 1 has a plurality of conductive bonding materials 226, and the wiring boards 100 and 200 are mechanically bonded to each other by the conductive bonding materials 226. The wiring boards 100 and 200 are electrically connected to each other through the conductive bonding materials 226. The conductive bonding materials 226 include solder, for example. Examples of the solder material include lead-free solder, such as tin-silver-based (SnAg-based) alloys, tin-zinc-based (SnZn-based) alloys, tin-copper-based (SnCu-based) alloys or the like, and lead-containing solder, such as lead-tin-based (PbSn-based) alloy, for example.

The wiring board 300 is provided on the wiring board 200. The laminated wiring board 1 has a plurality of conductive bonding materials 326, and the wiring boards 200 and 300 are mechanically bonded to each other by the conductive bonding materials 326. The wiring boards 200 and 300 are electrically connected to each other through the conductive bonding materials 326. A material used for the conductive bonding materials 326 may be the same as the material used for the conductive bonding materials 226, for example.

The wiring board 400 is provided on the wiring board 300. The laminated wiring board 1 has a plurality of conductive bonding materials 426, and the wiring boards 300 and 400 are mechanically bonded to each other by the conductive bonding materials 426. The wiring boards 300 and 400 are electrically connected to each other through the conductive bonding materials 426. A material used for the conductive bonding materials 426 may be the same as the material used for the conductive bonding materials 226, for example.

The wiring board 500 is provided on the wiring board 400. The laminated wiring board 1 has a plurality of conductive bonding materials 526, and the wiring boards 400 and 500 are mechanically bonded to each other by the conductive bonding materials 526. The wiring boards 400 and 500 are electrically connected to each other through the conductive bonding materials 526. A material used for the conductive bonding materials 526 may be the same as the material used for the conductive bonding materials 226, for example.

In the plan view, outer edges of the wiring boards 200, 300, 400, and 500 overlap each other. In addition, in the plan view, the outer edges of the wiring boards 200, 300, 400, and 500 are located inside an outer edge of the wiring board 100. In the plan view, a part of the upper surface of the wiring board 100 is exposed in an annular shape from the wiring boards 200, 300, 400, and 500. The wiring boards 200, 300, 400, and 500 are an example of first wiring boards, the wiring board 100 is an example of a second wiring board.

Next, the wiring boards 100, 200, 300, 400, and 500 will be described in more detail. FIG. 3A and FIG. 3B are cross sectional views illustrating examples of the wiring boards 100 and 200. FIG. 4A and FIG. 4B are cross sectional views illustrating examples of the wiring boards 300 and 400. FIG. 5 is a cross sectional view illustrating an example of the wiring board 500.

As illustrated in FIG. 3A, the wiring board 100 includes an interconnect layer 110, an insulating layer 111, an interconnect layer 112, an insulating layer 113, and an interconnect layer 114 that are successively laminated on one surface 101 a of a core layer 101. The wiring board 100 also includes an interconnect layer 120, an insulating layer 121, an interconnect layer 122, an insulating layer 123, an interconnect layer 124, and a solder resist layer 125 that are successively laminated on the other surface 101 b of the core layer 101.

A so-called glass epoxy substrate in which a glass cloth is impregnated with an insulating resin, such as an epoxy-based resin or a polyimide-based resin, for example, may be used for the core layer 101. A substrate in which a woven fabric or a nonwoven fabric of glass fiber, carbon fiber, aramid fiber, or the like, is impregnated with an epoxy-based resin or the like, for example, may also be used for the core layer 101. The core layer 101 may not include the glass cloth or the like.

The interconnect layer 110 is formed on the one surface 101 a of the core layer 101. The interconnect layer 110 is electrically connected to the interconnect layer 120 through via interconnects 102 penetrating the core layer 101. A material used for the interconnect layer 110 may be copper or the like, for example.

The insulating layer 111 is formed on the one surface 101 a of the core layer 101, so as to cover the interconnect layer 110. A material used for the insulating layer 111 may be an insulating resin or the like including an epoxy-based resin or a polyimide-based resin as a main component thereof, for example. A thickness of the insulating layer 111 may be in a range of approximately 10 μm to approximately 50 μm, for example. The insulating layer 111 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 112 is formed on one surface of the insulating layer 111. The interconnect layer 112 includes via interconnects filling via holes 111 x that penetrate the insulating layer 111 and expose the upper surface of the interconnect layer 110, and interconnect patterns famed on the upper surface of the insulating layer 111. The interconnect patterns of the interconnect layer 112 are electrically connected to the interconnect layer 110 through the via interconnects. Each via hole 111 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 110, for example. A material used for the interconnect layer 112 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 113 is formed on the upper surface of the insulating layer 111, so as to cover the interconnect layer 112. A material used for the insulating layer 113 and a thickness of the insulating layer 113 may be the same as those of the insulating layer 111, for example. The insulating layer 113 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 114 is formed on one surface of the insulating layer 113. The interconnect layer 114 includes via interconnects filling via holes 113 x that penetrate the insulating layer 113 and expose the upper surface of the interconnect layer 112, and interconnect patterns famed on the upper surface of the insulating layer 113. The interconnect patterns of the interconnect layer 114 are electrically connected to the interconnect layer 112 through the via interconnects. Each via hole 113 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 112, for example. A material used for the interconnect layer 114 may be the same as the material used for the interconnect layer 110, for example.

The interconnect layer 120 is formed on the other surface 101 b of the core layer 101. A material used for the interconnect layer 120 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 121 is formed on the other surface 101 b of the core layer 101, so as to cover the interconnect layer 120. A material used for the insulating layer 121 and a thickness of the insulating layer 121 may be the same as those of the insulating layer 111, for example. The insulating layer 121 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 122 is formed on the other surface of the insulating layer 121. The interconnect layer 122 includes via interconnects filling via holes 121 x that penetrate the insulating layer 121 and expose the lower surface of the interconnect layer 120, and interconnect patterns formed on the lower surface of the insulating layer 121. The interconnect patterns of the interconnect layer 122 are electrically connected to the interconnect layer 120 through the via interconnects. Each via hole 121 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 120, for example. A material used for the interconnect layer 122 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 123 is formed on the lower surface of the insulating layer 121, so as to cover the interconnect layer 122. A material used for the insulating layer 123 and a thickness of the insulating layer 123 may be the same as those of the insulating layer 111, for example. The insulating layer 123 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 124 is formed on the other surface of the insulating layer 123. The interconnect layer 124 includes via interconnects filling via holes 123 x that penetrate the insulating layer 123 and expose the lower surface of the interconnect layer 122, and interconnect patterns formed on the lower surface of the insulating layer 123. The interconnect patterns of the interconnect layer 124 are electrically connected to the interconnect layer 122 through the via interconnects. Each via hole 123 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 122, for example. A material used for the interconnect layer 124 may be the same as the material used for the interconnect layer 110, for example.

The solder resist layer 125 is the outermost layer on the other surface of the wiring board 100, and is an insulating layer provided on the lower surface of the insulating layer 123 so as to cover the interconnect layer 124. The solder resist layer 125 may be famed of a photosensitive resin or the like, such as an epoxy-based resin, an acrylic-based resin, or the like, for example. A thickness of the solder resist layer 125 may be in a range of approximately 5 μm to approximately 40 μm, for example.

The solder resist layer 125 has openings 125 x, and a part of the lower surface of the interconnect layer 124 is exposed at the bottom of the openings 125 x. The planar shape of the openings 125 x may be a circular shape, for example. The interconnect layer 124 exposed inside the openings 125 x can be used as pads for making electrical connections to a mounting substrate, such as a motherboard or the like. A metallic layer may be formed on the lower surface of the interconnect layer 124 exposed inside the openings 125 x, or the pads may be subjected to an anti-oxidation treatment, such as an organic solderability preservative (OSP) treatment or the like, as required.

As illustrated in FIG. 3B, the wiring board 200 includes an interconnect layer 210, an insulating layer 211, an interconnect layer 212, an insulating layer 213, and an interconnect layer 214 that are successively laminated on the one surface 201 a of a core layer 201. The wiring board 200 also includes an interconnect layer 220, an insulating layer 221, an interconnect layer 222, an insulating layer 223, and an interconnect layer 224 that are successively laminated on the other surface 201 b of the core layer 201.

A material used for the core layer 201 may be the same as the material used for the core layer 101, for example. The core layer 201 may not include the glass cloth or the like.

The interconnect layer 210 is formed on the one surface 201 a of the core layer 201. The interconnect layer 210 is electrically connected to the interconnect layer 220 through via interconnects 202 penetrating the core layer 201. A material used for the interconnect layer 210 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 211 is formed on the one surface 201 a of the core layer 201, so as to cover the interconnect layer 210. A material used for the insulating layer 211 and a thickness of the insulating layer 211 may be the same as those of the insulating layer 111, for example. The insulating layer 211 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 212 is formed on one surface of the insulating layer 211. The interconnect layer 212 includes via interconnects filling via holes 211 x that penetrate the insulating layer 211 and expose the upper surface of the interconnect layer 210, and interconnect patterns famed on the upper surface of the insulating layer 211. The interconnect patterns of the interconnect layer 212 are electrically connected to the interconnect layer 210 through the via interconnects. Each via hole 211 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 210, for example. A material used for the interconnect layer 212 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 213 is formed on the upper surface of the insulating layer 211, so as to cover the interconnect layer 212. A material used for the insulating layer 213 and a thickness of the insulating layer 213 may be the same as those of the insulating layer 111, for example. The insulating layer 213 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 214 is formed on one surface of the insulating layer 213. The interconnect layer 214 includes via interconnects filling via holes 213 x that penetrate the insulating layer 213 and expose the upper surface of the interconnect layer 212, and insulating layer 213. The interconnect patterns of the interconnect layer 214 are electrically connected to the interconnect layer 212 through the via interconnects. Each via hole 213 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 212, for example. A material used for the interconnect layer 214 may be the same as the material used for the interconnect layer 110, for example.

The interconnect layer 220 is formed on the other surface 201 b of the core layer 201. A material used for the interconnect layer 220 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 221 is formed on the other surface 201 b of the core layer 201, so as to cover the interconnect layer 220. A material used for the insulating layer 221 and a thickness of the insulating layer 221 may be the same as those of the insulating layer 111, for example. The insulating layer 221 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 222 is formed on the other surface of the insulating layer 221. The interconnect layer 222 includes via interconnects filling via holes 221 x that penetrate the insulating layer 221 and expose the lower surface of the interconnect layer 220, and interconnect patterns formed on the lower surface of the insulating layer 221. The interconnect patterns of the interconnect layer 222 are electrically connected to the interconnect layer 220 through the via interconnects. Each via hole 221 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 220, for example. A material used for the interconnect layer 222 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 223 is formed on the lower surface of the insulating layer 221, so as to cover the interconnect layer 222. A material used for the insulating layer 223 and a thickness of the insulating layer 223 may be the same as those of the insulating layer 111, for example. The insulating layer 223 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 224 is formed on the other surface of the insulating layer 223. The interconnect layer 224 includes via interconnects filling via holes 223 x that penetrate the insulating layer 223 and expose the lower surface of the interconnect layer 222, and interconnect patterns formed on the lower surface of the insulating layer 223. The interconnect patterns of the interconnect layer 224 are electrically connected to the interconnect layer 222 through the via interconnects. Each via hole 223 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 222, for example. A material used for the interconnect layer 224 may be the same as the material used for the interconnect layer 110, for example.

As illustrated in FIG. 4A, the wiring board 300 includes an interconnect layer 310, an insulating layer 311, and an interconnect layer 312 that are successively laminated on one surface 301 a of a core layer 301. The wiring board 300 also includes an interconnect layer 320, an insulating layer 321, and an interconnect layer 322 that are successively laminated on the other surface 301 b of the core layer 301.

A material used for the core layer 301 may be the same as the material used for the core layer 101, for example.

The interconnect layer 310 is formed on the one surface 301 a of the core layer 301. The interconnect layer 310 is electrically connected to the interconnect layer 320 through via interconnects 302 penetrating the core layer 301. A material used for the interconnect layer 310 may be the same as the material used for the interconnect layer 110, for example. The via interconnects 302 may be formed so as to cover an inner wall surface of via holes penetrating the core layer 301, and the insulating layer 303 may be provided inside the via interconnects 302.

The insulating layer 311 is formed on the one surface 301 a of the core layer 301, so as to cover the interconnect layer 310. A material used for the insulating layer 311 and a thickness of the insulating layer 311 may be the same as those of the insulating layer 111, for example. The insulating layer 311 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 312 is formed on one surface of the insulating layer 311. The interconnect layer 312 includes via interconnects filling via holes 311 x that penetrate the insulating layer 311 and expose the upper surface of the interconnect layer 310, and insulating layer 311. The interconnect patterns of the interconnect layer 312 are electrically connected to the interconnect layer 310 through the via interconnects. Each via hole 311 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 310, for example. A material used for the interconnect layer 312 may be the same as the material used for the interconnect layer 110, for example.

The interconnect layer 320 is formed on the other surface 301 b of the core layer 301. A material used for the interconnect layer 320 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 321 is formed on the other surface 301 b of the core layer 301, so as to cover the interconnect layer 320. A material used for the insulating layer 321 and a thickness of the insulating layer 321 may be the same as those of the insulating layer 111, for example. The insulating layer 321 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 322 is formed on the other side of the insulating layer 321. The interconnect layer 322 includes via interconnects filling via holes 321 x that penetrate the insulating layer 321 and expose the lower surface of the interconnect layer 320, and interconnect patterns famed on the lower surface of the insulating layer 321. The interconnect patterns of the interconnect layer 322 are electrically connected to the interconnect layer 320 through the via interconnects. Each via hole 321 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 320, for example. A material used for the interconnect layer 322 may be the same as the material used for the interconnect layer 110, for example.

As illustrated in FIG. 4B, the wiring board 400 includes an interconnect layer 410, an insulating layer 411, an interconnect layer 412, an insulating layer 413, and an interconnect layer 414 that are successively laminated on the one surface 401 a of a core layer 401. The wiring board 400 also includes an interconnect layer 420, an insulating layer 421, an interconnect layer 422, an insulating layer 423, and an interconnect layer 424 that are successively laminated on the other surface 401 b of the core layer 401.

A material used for the core layer 401 may be the same as the material used for the core layer 101, for example. The core layer 401 may not include the glass cloth or the like.

The interconnect layer 410 is formed on the one surface 401 a of the core layer 401. The interconnect layer 410 is electrically connected to the interconnect layer 420 through via interconnects 402 penetrating the core layer 401. A material used for the interconnect layer 410 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 411 is formed on the one surface 401 a of the core layer 401, so as to cover the interconnect layer 410. A material used for the insulating layer 411 and a thickness of the insulating layer 411 may be the same as those of the insulating layer 111, for example. The insulating layer 411 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 412 is formed on one surface of the insulating layer 411. The interconnect layer 412 includes via interconnects filling via holes 411 x that penetrate the insulating layer 411 and expose the upper surface of the interconnect layer 410, and interconnect patterns famed on the upper surface of the insulating layer 411. The interconnect patterns of the interconnect layer 412 are electrically connected to the interconnect layer 410 through the via interconnects. Each via hole 411 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 410, for example. A material used for the interconnect layer 412 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 413 is formed on the upper surface of the insulating layer 411, so as to cover the interconnect layer 412. A material used for the insulating layer 413 and a thickness of the insulating layer 413 may be the same as those of the insulating layer 111, for example. The insulating layer 413 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 414 is formed on one surface of the insulating layer 413. The interconnect layer 414 includes via interconnects filling via holes 413 x that penetrate the insulating layer 413 and expose the upper surface of the interconnect layer 412, and insulating layer 413. The interconnect patterns of the interconnect layer 414 are electrically connected to the interconnect layer 412 through the via interconnects. Each via hole 413 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 412, for example. A material used for the interconnect layer 414 may be the same as the material used for the interconnect layer 110, for example.

The interconnect layer 420 is formed on the other surface 401 b of the core layer 401. A material used for the interconnect layer 420 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 421 is formed on the other surface 401 b of the core layer 401, so as to cover the interconnect layer 420. A material used for the insulating layer 421 and a thickness of the insulating layer 421 may be the same as those of the insulating layer 111, for example. The insulating layer 421 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 422 is formed on the other surface of the insulating layer 421. The interconnect layer 422 includes via interconnects filling via holes 421 x that penetrate the insulating layer 421 and expose the lower surface of the interconnect layer 420, and interconnect patterns formed on the lower surface of the insulating layer 421. The interconnect patterns of the interconnect layer 422 are electrically connected to the interconnect layer 420 through the via interconnects. Each via hole 421 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 420, for example. A material used for the interconnect layer 422 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 423 is formed on the lower surface of the insulating layer 421, so as to cover the interconnect layer 422. A material used for the insulating layer 423 and a thickness of the insulating layer 423 may be the same as those of the insulating layer 111, for example. The insulating layer 423 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 424 is formed on the other surface of the insulating layer 423. The interconnect layer 424 includes via interconnects filling via holes 423 x that penetrate the insulating layer 423 and expose the lower surface of the interconnect layer 422, and interconnect patterns formed on the lower surface of the insulating layer 423. The interconnect patterns of the interconnect layer 424 are electrically connected to the interconnect layer 422 through the via interconnects. Each via hole 423 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 422, for example. A material used for the interconnect layer 424 may be the same as the material used for the interconnect layer 110, for example.

As illustrated in FIG. 5 , the wiring board 500 includes an interconnect layer 510, an insulating layer 511, an interconnect layer 512, an insulating layer 513, an interconnect layer 514, and a solder resist layer 515 that are successively laminated on one surface 501 a of a core layer 501. The wiring board 500 also includes an interconnect layer 520, an insulating layer 521, an interconnect layer 522, an insulating layer 523, and an interconnect layer 524 that are successively laminated on the other surface 501 b of the core layer 501.

A material used for the core layer 501 may be the same as the material used for the core layer 101, for example. The core layer 501 may not include the glass cloth or the like.

The interconnect layer 510 is formed on the one surface 501 a of the core layer 501. The interconnect layer 510 is electrically connected to the interconnect layer 520 through via interconnects 502 penetrating the core layer 501. A material used for the interconnect layer 510 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 511 is formed on the one surface 501 a of the core layer 501, so as to cover the interconnect layer 510. A material used for the insulating layer 511 and a thickness of the insulating layer 511 may be the same as those of the insulating layer 111, for example. The insulating layer 511 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 512 is formed on one surface of the insulating layer 511. The interconnect layer 512 includes via interconnects filling via holes 511 x that penetrate the insulating layer 511 and expose the upper surface of the interconnect layer 510, and interconnect patterns famed on the upper surface of the insulating layer 511. The interconnect patterns of the interconnect layer 512 are electrically connected to the interconnect layer 510 through the via interconnects. Each via hole 511 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 510, for example. A material used for the interconnect layer 512 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 513 is formed on the upper surface of the insulating layer 511, so as to cover the interconnect layer 512. A material used for the insulating layer 513 and a thickness of the insulating layer 513 may be the same as those of the insulating layer 111, for example. The insulating layer 513 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 514 is formed on one surface of the insulating layer 513. The interconnect layer 514 includes via interconnects filling via holes 513 x that penetrate the insulating layer 513 and expose the upper surface of the interconnect layer 512, and interconnect patterns famed on the upper surface of the insulating layer 513. The interconnect patterns of the interconnect layer 514 are electrically connected to the interconnect layer 512 through the via interconnects. Each via hole 513 x may be a cavity having an inverted truncated cone shape, and a diameter of an opening of the cavity at one end which opens upward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the upper surface of the interconnect layer 512, for example. A material used for the interconnect layer 514 may be the same as the material used for the interconnect layer 110, for example.

The solder resist layer 515 is the outermost layer on the one surface of the wiring board 500, and is an insulating layer provided on the upper surface of the insulating layer 513 so as to cover the interconnect layer 514. A material used for the solder resist layer 515 and a thickness of the solder resist layer 515 may be the same as those of the solder resist layer 125, for example.

The solder resist layer 515 has openings 515 x, and a part of the upper surface of the interconnect layer 514 is exposed at the bottom of the openings 515 x. The planar shape of the openings 515 x may be a circular shape, for example. A metallic layer may be famed on the upper surface of the interconnect layer 514 exposed inside the openings 515 x, or the exposed part of the upper surface of the interconnect layer 514 may be subjected to an anti-oxidation treatment, such as the OSP treatment or the like, as required.

External connection terminals 516 are formed on the upper surface of the interconnect layer 514 exposed at the bottom of the openings 515 x. The external connection terminals 516 may be solder bumps, for example. Examples of a material used for the solder bumps include alloys including Pb, alloys of Sn and Cu, alloys of Sn and Ag, alloys of Sn, Ag and Cu, or the like, for example. The external connection terminals 516 serve as terminals for making electrical connections to a semiconductor chip. The interconnect layer 520 is formed on the other surface 501 b of the core layer 501. A material used for the interconnect layer 520 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 521 is formed on the other surface 501 b of the core layer 501, so as to cover the interconnect layer 520. A material used for the insulating layer 521 and a thickness of the insulating layer 521 may be the same as those of the insulating layer 111, for example. The insulating layer 521 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 522 is formed on the other surface of the insulating layer 521. The interconnect layer 522 includes via interconnects filling via holes 521 x that penetrate the insulating layer 521 and expose the lower surface of the interconnect layer 520, and interconnect patterns formed on the lower surface of the insulating layer 521. The interconnect patterns of the interconnect layer 522 are electrically connected to the interconnect layer 520 through the via interconnects. Each via hole 521 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 520, for example. A material used for the interconnect layer 522 may be the same as the material used for the interconnect layer 110, for example.

The insulating layer 523 is formed on the lower surface of the insulating layer 521, so as to cover the interconnect layer 522. A material used for the insulating layer 523 and a thickness of the insulating layer 523 may be the same as those of the insulating layer 111, for example. The insulating layer 523 may include a filler, such as silica (SiO₂) or the like.

The interconnect layer 524 is formed on the other side of the insulating layer 523. The interconnect layer 524 includes via interconnects filling via holes 523 x that penetrate the insulating layer 523 and expose the lower surface of the interconnect layer 522, and interconnect patterns famed on the lower surface of the insulating layer 523. The interconnect patterns of the interconnect layer 524 are electrically connected to the interconnect layer 522 through the via interconnects. Each via hole 523 x may be a cavity having a truncated cone shape, and a diameter of an opening of the cavity at one end which opens downward is greater than a diameter of an opening of the cavity at the other end (that is, a bottom surface of the cavity) formed by the lower surface of the interconnect layer 522, for example. A material used for the interconnect layer 524 may be the same as the material used for the interconnect layer 110, for example.

The conductive bonding materials 226 mechanically bond and electrically connect the interconnect patterns of the interconnect layer 114 of the wiring board 100 and the interconnect patterns of the interconnect layer 224 of the wiring board 200 to one another. The conductive bonding materials 326 mechanically bond and electrically connect the interconnect patterns of the interconnect layer 214 of the wiring board 200 and the interconnect patterns of the interconnect layer 322 of the wiring board 300 to one another. The conductive bonding materials 426 mechanically bond and electrically connect the interconnect patterns of the interconnect layer 312 of the wiring board 300 and the interconnect patterns of the interconnect layer 424 of the wiring board 400 to one another. The conductive bonding materials 526 mechanically bond and electrically connect the interconnect patterns of the interconnect layer 414 of the wiring board 400 and the interconnect patterns of the interconnect layer 524 of the wiring board 500 to one another. The conductive bonding materials 326, 426, and 526 are an example of a first conductive bonding material, the conductive bonding materials 226 are an example of a second conductive bonding material.

The insulating resin layer 700 includes an adhesive portion 711, an adhesive portion 712, an adhesive portion 713, an adhesive portion 714, and a side surface covering portion 720. The adhesive portion 711 is provided between the upper surface of the wiring board 100 and the lower surface of the wiring board 200. The adhesive portion 711 adheres the wiring boards 100 and 200 to each other. The adhesive portion 712 is provided between the upper surface of the wiring board 200 and the lower surface of the wiring board 300. The adhesive portion 712 adheres the wiring boards 200 and 300 to each other. The adhesive portion 713 is provided between the upper surface of the wiring board 300 and the lower surface of the wiring board 400. The adhesive portion 713 adheres the wiring boards 300 and 400 to each other. The adhesive portion 714 is provided between the upper surface of the wiring board 400 and the lower surface of the wiring board 500. The adhesive portion 714 adheres the wiring boards 400 and 500 to each other. The side surface covering portion 720 covers a side surface of the wiring board 200, a side surface of the wiring board 300, a side surface of the wiring board 400, and a side surface of the wiring board 500. The side surface covering portion 720 further covers the upper surface of the wiring board 100 in an annular shape. For example, the adhesive portions 711, 712, 713, and 714 and the side surface covering portion 720 are integrated and unified. A material used for the insulating resin layer 700 may be an epoxy-based resin, for example. The adhesive portions 712, 713, and 714 are an example of a first insulating resin layer, the side surface covering portion 720 is an example of a second insulating resin layer, and the adhesive portion 711 is an example of a third insulating resin layer.

<Method for Manufacturing Laminated Wiring Board>

Next, a method for manufacturing the laminated wiring board according to the first embodiment will be described. FIG. 6A through FIG. 15 are diagrams illustrating an example of the method for manufacturing the laminated wiring board according to the first embodiment. FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, and FIG. are perspective views. FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG. 11A, and FIG. 11B through FIG. 15 are cross sectional views.

First, as illustrated in FIG. 6A through FIG. 10B, large wiring boards 100 t, 200 t, 300 t, 400 t, and 500 t are manufactured.

FIG. 6A is a perspective view of the large wiring board 100 t, and FIG. 6B is a cross sectional view of the large wiring board 100 t. The large wiring board 100 t includes a plurality of wiring board regions 100 s that becomes the wiring board 100 after singulation. FIG. 6B illustrates two wiring board regions 100 s. In the following description, the same names and reference numerals as those of the portions that are finally foamed on the wiring board 100 are used to describe the portions in the large wiring board 100 t.

When manufacturing the large wiring board 100 t, the via interconnects 102, the interconnect layer 110, and the interconnect layer 120 are first formed in the core layer 101. More particularly, the via holes are foamed in the core layer 101 by a laser beam machining using a CO₂ laser or the like, for example, and the via interconnects 102 are formed inside the via holes. In addition, the interconnect layer 110 is formed on the one surface 101 a of the core layer 101, and the interconnect layer 120 is formed on the other surface 101 b of the core layer 101, by the subtractive method or the like.

Next, the insulating layer 111 is formed by laminating a semi-cured film of an epoxy-based resin or the like on the one surface 101 a of the core layer 101, so as to cover the interconnect layer 110, and curing the film. The insulating layer 121 is formed by laminating a semi-cured film of an epoxy-resin or the like on the other surface 101 b of the core layer 101, so as to cover the interconnect layer 120, and curing the film. Alternatively, instead of laminating the film of the epoxy-based resin or the like, a liquid or paste of the epoxy-based resin or the like may be coated and thereafter cured, to form the insulating layers 111 and 121.

Next, the via holes 111 x that penetrate the insulating layer 111 and expose the upper surface of the interconnect layer 110 are formed in the insulating layer 111. In addition, the via holes 121 x that penetrate the insulating layer 121 and expose the lower surface of the interconnect layer 120 are formed in the insulating layer 121. The via holes 111 x and 121 x can be famed by the laser beam machining using the CO₂ laser or the like, for example. After forming the via holes 111 x and 121 x, it is preferable to perform a desmear process to remove resin residue adhered to the surfaces of the interconnect layers 110 and 120 exposed at the bottoms of the via holes 111 x and 121 x, respectively.

Next, the interconnect layer 112 is formed on the one surface of the insulating layer 111. The interconnect layer 112 includes the via interconnects filling the via holes 111 x, and the interconnect patterns formed on the upper surface of the insulating layer 111. Further, the interconnect layer 122 is formed on the other surface of the insulating layer 121. The interconnect layer 122 includes the via interconnects filling the via holes 121 x, and the interconnect patterns formed on the lower surface of the insulating layer 121. The interconnect layers 112 and 122 can be formed using various interconnect forming methods, such as the semi-additive method, the subtractive method, or the like.

For example, when the interconnect layer 112 is formed by the semi-additive method, a seed layer is formed by electroless plating of copper on the surface of the insulating layer 111 including the inner wall of the via holes 111 x and on the surface of the interconnect layer 110 exposed inside the via holes 111 x. Then, a plating resist pattern having openings corresponding to the shape of the interconnect patterns of the interconnect layer 112 is formed on the seed layer. Next, an electrolytic plating layer is deposited on the seed layer exposed inside the openings of the plating resist pattern by electrolytic plating of copper, using the seed layer as a power feeding layer. Then, the plating resist pattern is removed. Next, etching is performed using the electrolytic plating layer as a mask, to remove the seed layer exposed from the electrolytic plating layer. The interconnect layer 112 can be formed in this manner. The interconnect layer 122 can also be famed by the semi-additive method, similar to the interconnect layer 110.

After forming the interconnect layers 112 and 122, the insulating layer 113 is formed on the upper surface of the insulating layer 111 by a method similar to that used to foam the insulating layer 111, so as to cover the interconnect layer 112. Next, the via holes 113 x are formed by a method similar to that used to foam the via holes 111 x. Next, the interconnect layer 114 is formed on one surface of the insulating layer 113 by a method similar to that used to form the interconnect layer 112. In addition, the insulating layer 123 is famed on the lower surface of the insulating layer 121 by a method similar to that used to form the insulating layer 111, so as to cover the interconnect layer 122. Next, the via holes 123 x are formed by a method similar to that used to form the via holes 111 x. Next, the interconnect layer 124 is famed on the other surface of the insulating layer 123 by a method similar to that used to form the interconnect layer 112.

Next, the solder resist layer 125 is formed on the lower surface of the insulating layer 123, so as to cover the interconnect layer 124. The solder resist layer 125 can be formed by coating a liquid or a paste of a photosensitive epoxy-based resin or an acrylic-based resin on the lower surface of the insulating layer 123 by screen printing, roll coating, spin coating, or the like, for example, so as to cover the interconnect layer 124. Alternatively, a film of the photosensitive epoxy-based resin or the acrylic-based resin may be laminated on the lower surface of the insulating layer 123, for example, so as to cover the interconnect layer 124.

Next, by exposing and developing the solder resist layer 125, the openings 125 x that expose a part of the lower surface of the interconnect layer 124 are formed in the solder resist layer 125 by photolithography, for example. The openings 125 x may also be formed by the laser beam machining or a blasting. In this case, the photosensitive material does not need to be used for the solder resist layer 125.

The large wiring board 100 t can be manufactured in the manner described above.

FIG. 7A is a perspective view of the large wiring board 200 t, and FIG. 7B is a cross sectional view of the large wiring board 200 t. The large wiring board 200 t includes a plurality of wiring board regions 200 s that becomes the wiring board 200 after singulation. FIG. 7B illustrates two wiring board regions 200 s. In the following description, the same names and reference numerals as those of the portions that are finally formed on the wiring board 200 are used to describe the portions in the large wiring board 200 t.

When manufacturing the large wiring board 200 t, the via interconnects 202, the interconnect layer 210, and the interconnect layer 220 are first formed in the core layer 201. The via interconnects 202 can be formed by a method similar to that used to form the via interconnects 102, for example. The interconnect layers 210 and 220 can be famed by a method similar to that used to form the interconnect layer 110, for example.

Next, the insulating layer 211 is formed on the one surface 201 a of the core layer 201, so as to cover the interconnect layer 210, and the insulating layer 221 is formed on the other surface 201 b of the core layer 201, so as to cover the interconnect layer 220. The insulating layers 211 and 221 can be formed by a method similar to that used to form the insulating layer 111, for example. Further, the via holes 211 x are formed in the insulating layer 211, and the via holes 221 x are famed in the insulating layer 221. The via holes 211 x and 221 x can be formed by a method similar to that used to form the via holes 111 x, for example.

Next, the interconnect layer 212 is formed on the one surface of the insulating layer 211, and the interconnect layer 222 is formed on the other surface of the insulating layer 221. The interconnect layers 212 and 222 can be formed by a method similar to that used to foam the interconnect layer 112, for example.

Next, the insulating layer 213 is formed on the upper surface of the insulating layer 211, so as to cover the interconnect layer 212, and the insulating layer 223 is formed on the lower surface of the insulating layer 221, so as to cover the interconnect layer 222. The insulating layers 213 and 223 can be formed by a method similar to that used to form the insulating layer 111, for example. Further, the via holes 213 x are formed in the insulating layer 213, and the via holes 223 x are famed in the insulating layer 223. The via holes 213 x and 223 x can be formed by a method similar to that used to foam the via holes 111 x, for example.

Next, the interconnect layer 214 is formed on the one surface of the insulating layer 213, and the interconnect layer 224 is formed on the other surface of the insulating layer 223. The interconnect layers 214 and 224 can be formed by a method similar to that used to foam the interconnect layer 112, for example.

The large wiring board 200 t can be manufactured in the manner described above.

FIG. 8A is a perspective view of the large wiring board 300 t, and FIG. 8B is a cross sectional view of the large wiring board 300 t. The large wiring board 300 t includes a plurality of wiring board regions 300 s that becomes the wiring board 300 after singulation. FIG. 8B illustrates two wiring board regions 300 s. In the following description, the same names and reference numerals as those of the portions that are finally foamed on the wiring board 300 are used to describe the portions in the large wiring board 300 t.

When manufacturing the large wiring board 300 t, the via interconnects 302, the insulating layer 303, the interconnect layer 310, and the interconnect layer 320 are first formed in the core layer 301. The via interconnects 302 can be formed by a method similar to that used to foam the via interconnects 102, for example. The interconnect layers 310 and 320 can be formed by a method similar to that used to form the interconnect layer 110, for example. For example, the insulating layer 303 is famed so as to fill an inside of the via interconnects 302 in the via holes, after the via interconnects 302 are formed.

Next, the insulating layer 311 is formed on the one surface 301 a of the core layer 301, so as to cover the interconnect layer 310, and the insulating layer 321 is formed on the other surface 301 b of the core layer 301, so as to cover the interconnect layer 320. The insulating layers 311 and 321 can be formed by a method similar to that used to form the insulating layer 111, for example. Further, the via holes 311 x are formed in the insulating layer 311, and the via holes 321 x are famed in the insulating layer 321. The via holes 311 x and 321 x can be formed by a method similar to that used to foam the via holes 111 x, for example.

Next, the interconnect layer 312 is formed on the one surface of the insulating layer 311, and the interconnect layer 322 is formed on the other surface of the insulating layer 321. The interconnect layers 312 and 322 can be formed by a method similar to that used to foam the interconnect layer 112, for example.

The large wiring board 300 t can be manufactured in the manner described above.

FIG. 9A is a perspective view of the large wiring board 400 t, and FIG. 9B is a cross sectional view of the large wiring board 400 t. The large wiring board 400 t includes a plurality of wiring board regions 400 s that becomes the wiring board 400 after singulation. FIG. 9B illustrates two wiring board regions 400 s. In the following description, the same names and reference numerals as those of the portions that are finally formed on the wiring board 400 are used to describe the portions in the large wiring board 400 t.

When manufacturing the large wiring board 400 t, the via interconnects 402, the interconnect layer 410, and the interconnect layer 420 are first formed in the core layer 401. The via interconnects 402 can be formed by a method similar to that used to form the via interconnects 102, for example. The interconnect layers 410 and 420 can be famed by a method similar to that used to form the interconnect layer 110, for example.

Next, the insulating layer 411 is formed on the one surface 401 a of the core layer 401, so as to cover the interconnect layer 410, and the insulating layer 421 is formed on the other surface 401 b of the core layer 401, so as to cover the interconnect layer 420. The insulating layers 411 and 421 can be formed by a method similar to that used to form the insulating layer 111, for example. Further, the via holes 411 x are formed in the insulating layer 411, and the via holes 421 x are famed in the insulating layer 421. The via holes 411 x and 421 x can be formed by a method similar to that used to form the via holes 111 x, for example.

Next, the interconnect layer 412 is formed on the one surface of the insulating layer 411, and the interconnect layer 422 is formed on the other surface of the insulating layer 421. The interconnect layers 412 and 422 can be formed by a method similar to that used to foam the interconnect layer 112, for example.

Next, the insulating layer 421 is formed on the upper surface of the insulating layer 411, so as to cover the interconnect layer 412, and the insulating layer 423 is formed on the lower surface of the insulating layer 421, so as to cover the interconnect layer 422. The insulating layers 413 and 423 can be formed by a method similar to that used to form the insulating layer 111, for example. Further, the via holes 413 x are formed in the insulating layer 413, and the via holes 423 x are famed in the insulating layer 423. The via holes 413 x and 423 x can be formed by a method similar to that used to form the via holes 111 x, for example.

Next, the interconnect layer 414 is formed on the one surface of the insulating layer 413, and the interconnect layer 424 is formed on the other surface of the insulating layer 423. The interconnect layers 414 and 424 can be formed by a method similar to that used to foam the interconnect layer 112, for example.

The large wiring board 400 t can be manufactured in the manner described above.

FIG. 10A is a perspective view of the large wiring board 500 t, and FIG. 10B is a cross sectional view of the large wiring board 500 t. The large wiring board 500 t includes a plurality of wiring board regions 500 s that becomes the wiring board 500 after singulation. FIG. 10B illustrates two wiring board regions 500 s. In the following description, the same names and reference numerals as those of the portions that are finally famed on the wiring board 500 are used to describe the portions in the large wiring board 500 t.

When manufacturing the large wiring board 500 t, the via interconnects 502, the interconnect layer 510, and the interconnect layer 520 are first formed in the core layer 501. The via interconnects 502 can be formed by a method similar to that used to form the via interconnects 102, for example. The interconnect layers 510 and 520 can be famed by a method similar to that used to form the interconnect layer 110, for example.

Next, the insulating layer 511 is formed on the one surface 501 a of the core layer 501, so as to cover the interconnect layer 510, and the insulating layer 521 is formed on the other surface 501 b of the core layer 501, so as to cover the interconnect layer 520. The insulating layers 511 and 521 can be formed by a method similar to that used to form the insulating layer 111, for example. Further, the via holes 511 x are formed in the insulating layer 511, and the via holes 521 x are famed in the insulating layer 521. The via holes 511 x and 521 x can be formed by a method similar to that used to form the via holes 111 x, for example.

Next, the interconnect layer 512 is formed on the one surface of the insulating layer 511, and the interconnect layer 522 is formed on the other surface of the insulating layer 521. The interconnect layers 512 and 522 can be formed by a method similar to that used to foam the interconnect layer 112, for example.

Next, the insulating layer 513 is formed on the upper surface of the insulating layer 511, so as to cover the interconnect layer 512, and the insulating layer 523 is formed on the lower surface of the insulating layer 521, so as to cover the interconnect layer 522. The insulating layers 513 and 523 can be formed by a method similar to that used to form the insulating layer 111, for example. Further, the via holes 513 x are formed in the insulating layer 513, and the via holes 523 x are famed in the insulating layer 523. The via holes 513 x and 523 x can be formed by a method similar to that used to form the via holes 111 x, for example.

Next, the interconnect layer 514 is formed on the one surface of the insulating layer 513, and the interconnect layer 524 is formed on the other surface of the insulating layer 523. The interconnect layers 514 and 524 can be formed by a method similar to that used to foam the interconnect layer 112, for example.

The solder resist layer 515 is formed on the insulating layer 513, so as to cover the interconnect layer 514. The solder resist layer 515 can be formed by a method similar to that used to form the solder resist layer 125, for example.

Next, by exposing and developing the solder resist layer 515, the openings 515 x that expose a part of the upper surface of the interconnect layer 514 are formed in the solder resist layer 515 by photolithography, for example. The openings 515 x may also be formed by the laser beam machining or a blasting. In this case, the photosensitive material does not need to be used for the solder resist layer 515.

Next, the external connection terminals 516, such as solder bumps or the like, are famed on the upper surface of the interconnect layer 514 exposed at the bottom of the openings 515 x. The external connection terminals 516 serve as terminals for making electrical connections to the semiconductor chip.

The large wiring board 500 t can be manufactured in the manner described above.

After manufacturing the large wiring board 200 t, the conductive bonding materials 226 are famed on the lower surface of the interconnect layer 224, as illustrated in FIG. 11A. Further, an underfill layer 225 having fluidity is formed on the lower surface of the insulating layer 223, so as to cover the interconnect layer 224 and the conductive bonding materials 226. When forming the underfill layer 225, a film of an epoxy-based resin is laminated on the lower surface of the insulating layer 223, for example, so as to cover the interconnect layer 224 and the conductive bonding materials 226. The underfill layer 225 may be famed by coating a liquid or a paste of the epoxy-based resin on the lower surface of the insulating layer 223 by the screen printing, the roll coating, the spin coating, or the like, for example, so as to cover the interconnect layer 224 and the conductive bonding materials 226. The underfill layer 225 is an example of a second fluid insulating resin layer.

After manufacturing the large wiring board 300 t, the conductive bonding materials 326 are famed on the lower surface of the interconnect layer 322, as illustrated in FIG. 11B. Further, an underfill layer 325 having fluidity is formed on the lower surface of the insulating layer 321, so as to cover the interconnect layer 322 and the conductive bonding materials 326. The underfill layer 325 can be famed by a method similar to that used to form the underfill layer 225, for example. The underfill layer 325 is an example of a first fluid insulating resin layer.

After manufacturing the large wiring board 400 t, the conductive bonding materials 426 are famed on the lower surface of the interconnect layer 424, as illustrated in FIG. 12A. Further, an underfill layer 425 having fluidity is formed on the lower surface of the insulating layer 423, so as to cover the interconnect layer 424 and the conductive bonding materials 426. The underfill layer 425 can be famed by a method similar to that used to form the underfill layer 225, for example. The underfill layer 425 is an example of the first fluid insulating resin layer.

After manufacturing the large wiring board 500 t, the conductive bonding materials 526 are famed on the lower surface of the interconnect layer 524, as illustrated in FIG. 12B. Further, an underfill layer 525 having fluidity is formed on the lower surface of the insulating layer 523, so as to cover the interconnect layer 524 and the conductive bonding materials 526. The underfill layer 525 can be famed by a method similar to that used to form the underfill layer 225, for example. The underfill layer 525 is an example of the first fluid insulating resin layer.

Thereafter, as illustrated in FIG. 13 , the large wiring board 100 t is singulated into individual wiring board regions 100 s to obtain a plurality of wiring boards 100. The large wiring board 200 t on which the conductive bonding materials 226 and the underfill layer 225 are formed is singulated for each wiring board region 200 s to obtain a plurality of wiring boards 200 on which the conductive bonding materials 226 and the underfill layer 225 are formed. The large wiring board 300 t on which the conductive bonding materials 326 and the underfill layer 325 are formed is singulated for each wiring board region 300 s to obtain a plurality of wiring boards 300 on which the conductive bonding materials 326 and the underfill layer 325 are formed. The large wiring board 400 t on which the conductive bonding materials 426 and the underfill layer 425 are formed is singulated for each wiring board region 400 s to obtain a plurality of wiring boards 400 on which the conductive bonding materials 426 and the underfill layer 425 are formed. The large wiring board 500 t on which the conductive bonding materials 526 and the underfill layer 525 are formed is singulated for each wiring board region 500 s to obtain a plurality of wiring boards 500 on which the conductive bonding materials 526 and the underfill layer 525 are formed.

Next, the wiring board 100 having predetermined characteristics is selected from the plurality of wiring boards 100, the wiring board 200 having predetermined characteristics is selected from the plurality of wiring boards 200, and the wiring board 300 having predetermined characteristics is selected from the plurality of wiring boards 300. In addition, the wiring board 400 having predetermined characteristics is selected from the plurality of wiring boards 400, and the wiring board 500 having predetermined characteristics is selected from the plurality of wiring boards 500. Then, the selected wiring boards 200, 300, 400, and 500 having the predetermined characteristics are successively laminated in this order on the selected wiring board 100 having the predetermined characteristics, to thereby obtain a laminated body 10. Determining whether or not each wiring board has the predetermined characteristics may be performed before or after the singulation. However, when forming the laminated body 10, non-defective products (wiring boards having the predetermined characteristics) are selected, and the non-defective products are combined with one another.

Next, the laminated body 10 is subjected to a temporary compression bonding. In the temporary compression bonding, the laminated body 10 is heated while applying pressure from above and below the laminated body 10. As a result, as illustrated in FIG. 14 , the underfill layers 225, 325, 425, and 525 are compressed and protrude from the side surfaces of the laminated body of the wiring boards 200, 300, 400, and 500. Further, the conductive bonding materials 226, 326, 426, and 526 are also compressed.

Next, the laminated body 10 is subjected to a main compression bonding. In the main compression bonding, the laminated body 10 is heated while applying pressure from above, below, and the side of the laminated body 10, in a state where the laminated body 10 is covered from above with a diaphragm rubber. As a result, as illustrated in FIG. 15 , the underfill layers 225, 325, 425, and 525 are further compressed, and the portions protruding from the side surfaces of the laminated body of the wiring boards 200, 300, 400, and 500 are integrated and unified on the inner side of the diaphragm rubber. As a result, the insulating resin layer 700, including the adhesive portions 711, 712, 713, and 714, and the side surface covering portion 720, is formed.

Moreover, in the main compression bonding, the conductive bonding materials 226, 326, 426, and 526 are melted and solidified. As a result, the wiring board 100 and the wiring board 200 are mechanically bonded to each other by the conductive bonding materials 226, the wiring board 200 and the wiring board 300 are mechanically bonded to each other by the conductive bonding materials 326, the wiring board 300 and the wiring board 400 are mechanically bonded to each other by the conductive bonding materials 426, and the wiring boards 400 and the wiring board 500 are mechanically bonded to each other by the conductive bonding materials 526.

The laminated wiring board 1 according to the first embodiment can be manufactured in the manner described above.

The laminated wiring board 1 includes a plurality of interconnect layers. When forming the interconnect layers, a portion that does not satisfy the predetermined characteristics may be generated. Accordingly, as the number of interconnect layers formed on the large wiring board including a plurality of wiring board regions increases, the number of wiring boards having the predetermined characteristics among the plurality of wiring boards formed from the large wiring board decreases.

In the present embodiment, the number of interconnect layers included in the laminated wiring board 1 is 28, but the number of interconnect layers included in each of the large wiring boards 100 t, 200 t, 400 t, and 500 t is 6, and the number of interconnect layers included in the large wiring board 300 t is 4. For this reason, it is possible to considerably improve the yield compared to a case where the large wiring board including 28 interconnect layers is manufactured by the build-up method.

In addition, when compared to the case where the large wiring board including 28 interconnect layers is used, the proportion of defects generated from each large wiring board is low, and it is thus possible to increase the number of laminated wiring boards 1 having predetermined characteristics that can be manufactured per unit time, such as one month, for example. That is, the throughput can be improved.

Further, the lead time can be shortened by performing at least a part of the manufacturing processes of the large wiring boards 100 t, 200 t, 300 t, 400 t, and 500 t in parallel.

In the present embodiment, the side surface covering portion 720 covers the side surfaces of the wiring boards 200, 300, 400, and 500. For this reason, it is possible to reduce delamination of the wiring boards from one another, and to reduce delamination of the insulating layer and the interconnect layer in each of the wiring boards. For example, the temperature of the laminated wiring board 1 may increase when the semiconductor chip is mounted on the laminated wiring board 1, or during the use of the laminated wiring board 1. Further, the laminated wiring board 1 may be heated during a reliability test. When the temperature of the laminated wiring board 1 rises, a thermal stress may be generated in the laminated wiring board 1. In the present embodiment, even if the thermal stress is generated, the delamination caused by the thermal stress can be reduced.

Melting points of the conductive bonding materials 226, 326, 426, and 526 are preferably lower than a melting point of the external connection terminals 516. This is because the conductive bonding materials 226, 326, 426, and 526 can be melted without melting the external connection terminals 516 during the main compression bonding. In a case where the melting point of the external connection terminals 516 is lower than or equal to the melting points of the conductive bonding materials 226, 326, 426, and 526, for example, the external connection terminals 516 can be formed after the main compression bonding.

The outer edges of the wiring boards 200, 300, 400, and 500 do not need to overlap one another in the plan view, and the outer edges of the wiring boards 200, 300, 400, and 500 may be deviated from one another. Even in such a case, the outer edges of the wiring boards 200, 300, 400, and 500 are preferably located inside the outer edge of the wiring board 100 in the plan view, because it becomes easier to stably form the side surface covering portion 720.

Second Embodiment

<Configuration of Laminated Wiring Board>

Next, a second embodiment will be described. FIG. 16 is a top view illustrating an example of the laminated wiring board according to the second embodiment. FIG. 17 is a cross sectional view illustrating the example of the laminated wiring board according to the second embodiment. FIG. 17 corresponds to a cross sectional view along a line XVI-XVI in FIG. 16 .

As illustrated in FIG. 16 and FIG. 17 , a laminated wiring board 2 according to the second embodiment includes a resin outflow restriction member 800 provided on the wiring board 100 and surrounding the side surface covering portion 720 in the plan view. Similar to the first embodiment, the side surface covering portion 720 covers the side surface of the wiring board 200, the side surface of the wiring board 300, the side surface of the wiring board 400, and the side surface of the wiring board 500. In the plan view, an outer edge of the side surface covering portion 720 is in contact with the resin outflow restriction member 800. A material used for the resin outflow restriction member 800 may be an epoxy-based resin or solder resist, for example.

Other configurations of the second embodiment are the same as those of the first embodiment.

<Method for Manufacturing Laminated Wiring Board>

When manufacturing the laminated wiring board 2 according to the second embodiment, the resin outflow restriction member 800 is formed on the wiring board 100, surrounding a region where the wiring boards 200, 300, 400, and 500 are laminated, so as to be separated from the region in the plan view, before foaming the laminated body such as before the temporary compression bonding, for example. The resin outflow restriction member 800 can be formed by curing a photoresist, for example.

Other processes performed to manufacture the second embodiment are the same as those performed to manufacture the first embodiment.

In the second embodiment, the resin outflow restriction member 800 is formed before the laminated body is compression bonded. For this reason, an outflow range of the underfill layers 225, 325, 425, and 525 during the compression bonding is restricted, and it is possible to more easily obtain a stable shape of the side surface covering portion 720.

Third Embodiment

Next, a third embodiment will be described. FIG. 18 is a cross sectional view illustrating an example of the laminated wiring board according to a third embodiment. As illustrated in FIG. 18 , a laminated wiring board 3 according to the sixth embodiment does not include the wiring board 100, and the wiring board 200 includes a solder resist layer 227. The solder resist layer 227 is the outermost layer on the other surface of the wiring board 200, and is an insulating layer provided on the lower surface of the insulating layer 223 so as to cover the interconnect layer 224. A material used for the solder resist layer 227 and a thickness of the solder resist layer 227 may be the same as those of the solder resist layer 125, for example.

The solder resist layer 227 has openings 227 x, and a part of the lower surface of the interconnect layer 224 is exposed at the bottom of the openings 227 x. The planar shape of the openings 227 x is a circular shape, for example. The interconnect layer 224 exposed inside the openings 227 x can be used as pads for making electrical connections to the mounting substrate, such as the mother board or the like. A metallic layer may be formed on the lower surface of the interconnect layer 224 exposed inside the openings 227 x, or the pads may be subjected to an anti-oxidation treatment, such as the OSP treatment or the like, as required.

The insulating resin layer 700 may not include the adhesive portion 711, and the side surface covering portion 720 may cover a side surface of the solder resist layer 227.

According to the third embodiment, it is possible to obtain effects similar to those obtainable in the first embodiment.

In the present disclosure, the number of wiring boards included in the laminated wiring board is not particularly limited, as long as the number is two or greater. Further, the number of interconnect layers included in each wiring board is also not particularly limited.

According to the disclosed technique, it is possible to reduce deterioration of the yield.

Various aspects of the subject-matter described herein may be set out non-exhaustively in the following numbered clauses:

1. A method for manufacturing a laminated wiring board, comprising:

-   -   foaming a plurality of first wiring boards;     -   foaming a laminated body by laminating the plurality of first         wiring boards on one another while providing a first fluid         insulating resin layer therebetween; and compression bonding the         laminated body,     -   wherein the compression bonding includes         -   forming a first insulating resin layer disposed between two             adjacent first wiring boards among the plurality of first             wiring boards using the first fluid insulating resin layer;             and         -   forming a second insulating resin layer covering side             surfaces of the plurality of first wiring boards using the             first fluid insulating resin layer.

2. The method for manufacturing the laminated wiring board according to clause 1, further comprising:

-   -   foaming a second wiring board, wherein     -   the forming the laminated body includes laminating the plurality         of first wiring boards on the second wiring board while         providing a second fluid insulating resin layer between a first         wiring board closest to the second wiring board among the         plurality of first wiring boards, and the second wiring board,         and     -   the compression bonding includes forming a third insulating         resin layer disposed between the second wiring board and the         first wiring board closest to the second wiring board using the         second fluid insulating resin layer.

3. The method for manufacturing the laminated wiring board according to clause 2, further comprising:

-   -   foaming a resin outflow restriction member on the second wiring         board, surrounding a region where the plurality of first wiring         boards is laminated, so as to be separated from the region in a         plan view, before the compression bonding.

Although the embodiments are numbered with, for example, “first,” “second,” or “third,” the ordinal numbers do not imply priorities of the embodiments. Many other variations and modifications will be apparent to those skilled in the art.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A laminated wiring board comprising: a plurality of first wiring boards laminated on one another; a first insulating resin layer disposed between two adjacent first wiring boards among the plurality of first wiring boards; and a second insulating resin layer configured to cover side surfaces of the plurality of first wiring boards.
 2. The laminated wiring board as claimed in claim 1, wherein the first insulating resin layer and the second insulating resin layer are integrated and unified.
 3. The laminated wiring board as claimed in claim 1, further comprising: a first conductive bonding material configured to bond the plurality of first wiring boards to one another.
 4. The laminated wiring board as claimed in claim 1, further comprising: a second wiring board, wherein the plurality of first wiring boards is laminated on the second wiring board; and a third insulating resin layer disposed between a first wiring board closest to the second wiring board among the plurality of first wiring boards, and the second wiring board.
 5. The laminated wiring board as claimed in claim 4, wherein the second insulating resin layer and the third insulating resin layer are integrated and unified.
 6. The laminated wiring board as claimed in claim 4, further comprising: a second conductive bonding material configured to bond a first wiring board closest to the second wiring board among the plurality of first wiring boards, and the second wiring board.
 7. The laminated wiring board as claimed in claim 4, further comprising: a resin outflow restriction member provided on the second wiring board and surrounding the second insulating resin layer in a plan view.
 8. The laminated wiring board as claimed in claim 1, wherein the second insulating resin layer completely covers the side surfaces of the plurality of first wiring boards.
 9. The laminated wiring board as claimed in claim 1, wherein each first wiring board among the plurality of first wiring boards has a configuration including a laminate of a plurality of insulating layers and a plurality of interconnect layers. 